1. Field of the Invention
The present invention relates to the field of finite state machines.
2. Prior Art
A finite state machine (FSM) is a commonly used technique in logical processing devices. In integrated circuits, FSMs are usually built using programmed logic arrays (PLA).
One method for implementing such an FSM involves the use of a constantly active pull-up device in the PLA. A constantly active pull-up will draw current at all times that power is being supplied to the circuit. This technique results in excessive D.C. current consumption. Excessive current consumption in integrated circuits causes the device to generate unwanted heat resulting in component reliability problems. Further, excessive current consumption in individual components creates system design problems because of the limitations imposed on remote site battery applications, as well as the necessity to increase system power bus capacity and signal shielding requirements.
Another method for implementing such an FSM involves the use of precharge/selective discharge circuitry. This technique requires more stringent timing specifications. These more stringent timing requirements create the need for complicated circuitry. Generally, the system clock must either be split into two phases or an additional clock signal must be supplied in order to implement a precharge/selective discharge PLA circuit. Such complex circuitry often creates manufacturing and yield problems. Prior approaches to solving the FSM design clearly contain inherent problems.